Difference between revisions of "KFLOP Hardware Info"
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| width="260"|<span style="font-family: Arial Black; font-size: small;">[http://dynomotion.com/Help/VirtualComPortwithKFLOP.pdf Virtual COM Port Driver Installation]</span> | | width="260"|<span style="font-family: Arial Black; font-size: small;">[http://dynomotion.com/Help/VirtualComPortwithKFLOP.pdf Virtual COM Port Driver Installation]</span> | ||
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| + | ==Hardware Topics== | ||
| + | [[Noise - Typical Problems and Resolutions|Dealing with noise using KFLOP input filters]] | ||
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| + | ==KFLOP Inputs Floating High== | ||
| + | A common question is: '''''"I don't have a KFLOP Input Connected to anything. Why is it reading high?"''''' | ||
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| + | If a KFLOP input is not connected then it may float to any voltage. KFLOP inputs (those without pull down resistors) are very high impedance (many megohms). The slightest leakage current due to moisture, parasitic inductance, capacitance, etc can make the voltage non zero. Often a ribbon cable will cause one floating input to follow an adjacent signal in the cable that is being driven. | ||
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| + | KFLOP inputs are voltage sensitive and require almost zero current. Unlike something like a light bulb that requires significant current and will go to 0V and off if disconnected. KFLOP Inputs must be driven high (>2.0V) and low (< 0.4V). If not driven they may be high or low. | ||
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| + | A simple switch can not normally be used to drive a KFLOP input because when the switch is open it will float to any state. An exception to this is the 16 KFLOP inputs on JP4 and JP5 that have 150ohm pull down resistors. Those will be guaranteed to be low if disconnected. So a simple switch to 3.3V might be used to drive those. | ||
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| + | KFLOP inputs are all 3.3V LVTTL and have protection diodes connected to the 3.3V power supply (and GND) to prevent the input from floating too high (from leakage or static electricity) and burning out. For this reason KFLOP inputs should never be driven higher than 3.8V. Because of the internal construction of the FPGA (where differential pairs share some common circuitry) if an input is driven high enough to be forced to clamp, some clamping current may leak into the complimentary signal pair input. This should be avoided. | ||
Latest revision as of 19:05, 10 January 2018
KFLOP - DSP-based microcontroller with 1.2 GFLOPs of processing power, a 100k Gate FPGA, 16 Mb SDRAM, 8 axes of control, lots of I/O and the ability to program in C
| Summary | |
| HW/SW Specification | |
| Block Diagram | |
| Analog IO Screen | Digital IO Screen |
| Functional Diagram | Virtual COM Port Driver Installation |
Hardware Topics
Dealing with noise using KFLOP input filters
KFLOP Inputs Floating High
A common question is: "I don't have a KFLOP Input Connected to anything. Why is it reading high?"
If a KFLOP input is not connected then it may float to any voltage. KFLOP inputs (those without pull down resistors) are very high impedance (many megohms). The slightest leakage current due to moisture, parasitic inductance, capacitance, etc can make the voltage non zero. Often a ribbon cable will cause one floating input to follow an adjacent signal in the cable that is being driven.
KFLOP inputs are voltage sensitive and require almost zero current. Unlike something like a light bulb that requires significant current and will go to 0V and off if disconnected. KFLOP Inputs must be driven high (>2.0V) and low (< 0.4V). If not driven they may be high or low.
A simple switch can not normally be used to drive a KFLOP input because when the switch is open it will float to any state. An exception to this is the 16 KFLOP inputs on JP4 and JP5 that have 150ohm pull down resistors. Those will be guaranteed to be low if disconnected. So a simple switch to 3.3V might be used to drive those.
KFLOP inputs are all 3.3V LVTTL and have protection diodes connected to the 3.3V power supply (and GND) to prevent the input from floating too high (from leakage or static electricity) and burning out. For this reason KFLOP inputs should never be driven higher than 3.8V. Because of the internal construction of the FPGA (where differential pairs share some common circuitry) if an input is driven high enough to be forced to clamp, some clamping current may leak into the complimentary signal pair input. This should be avoided.
