Not getting 3v3 PWM output on JP6 pin 5 (IO26)

[SJHardy]

Hopefully a quick one: I expected IO26/PWM0 to be a push-pull drive, so should get 3.3V pk-pk, however we are seeing only about 2.3V pk-pk, and about 200mV of noise on top of that, during the high output state. Only noticed recently because mostly we have fairly slow spindles, but the one we are using now is more responsive so it's easier to hear the speed fluctuations.

So question is, am I doing something wrong to (say) configure it as open drain output? Or is it always open drain?

I filter the PWM using 10kOhm/4.7uF RC filter, followed by a 4x non-inverting op amp, to give 0-10V (really, 0-13.3V but the max PWM duty can be configured to max it out at 10V). Max load on the Kflop output would be 3.3V/10k = 330uA.

I would think that, even if that is too much current sourcing, I wouldn't be seeing that much drop or so much noise.

Any ideas?

Regards,
SJH

[TomKerekes]

Hi SJH,

The PWM outputs are always push-pull type outputs. The high level voltage is relatively low because those IO have 150 Ohm termination for use as inputs. There is no specification on the high/low levels other than they meet minimum LVTTL requirements and are not necessarily consistent. The only thing guaranteed would be the timing. Can you add a switch to a reference voltage level?

[SJHardy]

So, not a software fix. Oh dear.

Is the actual driving chip TTL, or is it CMOS pretending to be TTL? I assumed when designing our breakout board that it was CMOS and hence high and low levels would be very close to supply if terminated by infinite impedance (regardless of conservative manufacturer specs). But I guess if it was a true bipolar output then there could be a voltage drop (e.g. if emitter follower you get a Vbe drop).

I tested on other boards. High state voltage varies between 2.1 and 3.0V.

Could the driver chip be generating its own internal rail at a lower voltage, maybe to better conform with LVTTL spec?

The output filter will present megohm level impedance if the output duty is 100%, since the filter cap will be charged to same voltage, and the opamp input bias is 1uA or less. But the high state output is ~2.1V no matter what duty is being output.

Not sure what you mean by adding a switch, but it might be interesting to add a 1k pullup.

One weird thing is that the audible fluctuation in spindle speed (maybe about 5%) depends on what other unrelated axis moves are going on, and if I hit the feed hold button at the right point the current speed is "locked in" and doesn't audibly change, but then starts again when f/h is released.

Scoping it shows maybe about 60KHz sine wave noise. Maybe that's coming from an on-board SMPS supplying one of the lower rails.

[SJHardy]

The J2 jumper sets 2.5/3.3V for "comm". Would that affect the PWM outputs too?

[TomKerekes]

Is the actual driving chip TTL, or is it CMOS pretending to be TTL? I assumed when designing our breakout board that it was CMOS and hence high and low levels would be very close to supply if terminated by infinite impedance (regardless of conservative manufacturer specs). But I guess if it was a true bipolar output then there could be a voltage drop (e.g. if emitter follower you get a Vbe drop).

They are MOSFET outputs directly from the FPGA, but with external 150 Ohm pull down resistors.

Could the driver chip be generating its own internal rail at a lower voltage, maybe to better conform with LVTTL spec?

The J2 jumper sets 2.5/3.3V for "comm". Would that affect the PWM outputs too?

The FPGA has its IO divided into 4 sections. Each section can have its own Voltage supply. It doesn't generate any internal voltages. KFLOP has 3 sections hard wired to the 3.3V supply. Section 1 has a jumper (J2) for 3.3V or 2.5V. The jumper should always be between pins 1 and 2 for 3.3V. JP5 and JP6 IO use section 1 FPGA IO. Is the J2 jumper removed or installed incorrectly?

[SJHardy]

I didn't realize the 150 ohms were pull-downs, I assumed they were series termination. That explains the lower voltage. It seems we get about 300mV drop from the rail.

Our guys doing the board assembly normally put the jumper for 3v3, but it's possible that mistakes were made in which case it would explain the 2.2V output. With all the board swapping while trying to figure this out, it's a bit confused now. That board might also have had an injury during assembly - it seems functional but now bets are off.

The good news is that we used another Kflop and it's working fine now.

Thanks for the help,
SJH