0-5V output from KSTEP

[Guarduaro]

Hello,
I cannot figure out why I cannot get a 0-5V output out of the Kstep to run my spindle speed. Here is my setup...
Setup:
Kflop connected to Kstep and Konnect
Connections:
+5Vdc from spindle control power supply to JP33 Pin5 (AnalogVcc)
JP33 Pin6 (AnalogOut) to spindle control analog input (expect 0-5V)
Test Program
CProgram:
{
FPGA(KAN_TRIG_REG) = 4;
SetBitDirection(44,1);
FPGA(IO_PWMS_PRESCALE) = 32;
FPGA(IO_PWMS) = 128;
FPGA(IO_PWMS+1) = 1;
}
I have varied the square wave and the frequency and voltage is constantly high.
I also tried a second Kstep board with the same results.
What am I doing wrong?

[TomKerekes]

Hi,

You likely need an Analog GND connection. KStep's Analog IO is fully isolated.

[Guarduaro]

Here is how I have it wired...

Spindle PS +5V to JP33-5
JP33-6 to Spindle Analog +
Spindle PS GND to Analog GND

Any other thoughts?

Thanks,
Jerry

[TomKerekes]

Hi Jerry,

I can't see why that wouldn't work. You might troubleshoot to find where the problem lies.

After a KFLOP Power cycle, before configuring anything, IO44 should have no drive, be low, and cause the Analog Output to be driven low. Check if this is the case.

If low, you might set IO44 as an output using the Digital IO Screen and toggle the state. Check if the Analog Output toggles between nearly +5V and GND. Note Your meter must be referencing Analog GND.

Regards

[Guarduaro]

Tom,

So I took the spindle out of the picture by feed the analog output to a signal conditioner and no change.

Here is the setup with the signal conditioner.

Signal Conditioner: 0-5Vdc input and 0-5Vdc output

+5V from 5Vdc power supply to JP33-5
JP33-6 to V+ input to signal conditioner
0V from 5Vdc power supply to COM of input to signal conditioner

I measured the voltage across the input to the signal conditioner which is the same results when connected to the spindle.

What am I missing?

Thanks,
Jerry

[Guarduaro]

Tom,

I restarted the system, with no program I measured JP33-6 has 3.95V (JP33-5 has measured 5V)
Toggling IO44 to on in the digital IO window the voltage slightly increases to 4.1V.

Thanks,
Jerry

[TomKerekes]

Hi Jerry,

I'm not sure what a "signal conditioner" is.

It isn't clear to me that you have an Analog GND connection from KStep JP33 pin 7 to the 5VDC power supply GND. Or where your meter GND is connected. Maybe draw a diagram.

I like the idea to eliminate the Spindle from the picture. Just apply a voltage such as a +9V battery to Analog Vcc (pin5) and Analog GND (pin7). Then measure Analog Out (pin6) with a volt meter relative to battery GND. Then perform the test in my previous email.

Regards

[Guarduaro]

Tom,

I really appreciate your time and assistance!!

I really love the Dynomotion system! And your responsiveness!

So my mistake was not connecting JP33-7 to PS ground. I looked at the KStep connector info but interpreted that if I was using it as a pot simulation I would need to connect the PS ground to pin7. I attached a wiring diagram...

So one more question, my preference would be to use a PWM output, however it appears that only an analog output is available through JP33. Am I correct? If not, what would be the connectivity.

Thanks,
Jerry

[TomKerekes]

Hi Jerry,

Thanks for your patience.

So one more question, my preference would be to use a PWM output, however it appears that only an analog output is available through JP33. Am I correct? If not, what would be the connectivity.

KFLOP has eight 8-bit PWM outputs on KFLOP JP6. They are non-isolated LVTTL signals. What is the voltage level, frequency, and isolation requirements for the PWM signal you need?

PWM0 is what is used by KStep to create the analog signal. The C Program command FPGA(KAN_TRIG_REG) = 4; is what move the single PWM0 signal from JP6 to JP7 so it can be used by KStep. If you don't use that command it will remain on JP6 IO26 pin 5.

HTH