--- In DynoMotion@yahoogroups.com, Tom Kerekes <tk@...> wrote:
>
> Hi Kevin,
>
> Heh heh, I tried unrolling the loop and it made it slightly worse.  I guess it doesn't fit in cache or something.
>
> Writing directly to hard coded FPGA addresses to set/clear the bits, placing the code in internal DSP memory, using an optimizing compiler reduced it to the 10us.  But it would be hard to write this in a general way.
>
> There is also a way in KFLOP to set or clear multiple bits at the same time with one IO operation.  Potentially something like the data set and clock set might be done together, but that wouldn't help if the data was low. 
>
> External IO from the DSP is relatively slow.  It surprises me that the time to read an IO bit is about the same time as theoretically to do 50+ 32-bit floating point operations.
>
>
> Regards
> TK
>
>
>
> ________________________________
> From: fireup_kev <kliboon@...>
> To: DynoMotion@yahoogroups.com
> Sent: Sunday, April 7, 2013 10:03 AM
> Subject: [DynoMotion] Re: SPI
>
>
>  
> I'm using it for many things. One is to expand the I/O and the other is to read external memory. The chips can run at 20 MHz or more and I would like to take advantage of that if I can. 450KHz is decent for now but will make me rethink if I should add other stuff to the bus.
>
> Thanks for the benchmark routine. I'll try unrolling the loop to see if there's any improvements.
>
> Thanks,
> Kevin
>
> --- In DynoMotion@yahoogroups.com, Tom Kerekes <tk@> wrote:
> >
> > Hi Kevin,
> >
> > I measure about 18us to send a byte (which is ~ 450KHz clock rate).  See attached benchmark.  Results:
> >
> > Times 25.360000 17.800000 17.960000 41.745960 us
> >
> > First one take a bit longer to fill the cache, next two take about 18us, average of 1000 takes longer because of time slicing the thread only gets ~1/3 of the CPU.
> >
> >
> > It looks like with some tricky code it could be reduced to ~10us.
> >
> > Can you say what you are using it for?
> >
> > Regards
> > TK
> >
> >
> >
> >
> >
> > ________________________________
> > From: fireup_kev <kliboon@>
> > To: DynoMotion@yahoogroups.com
> > Sent: Friday, April 5, 2013 12:58 PM
> > Subject: [DynoMotion] Re: SPI
> >
> >
> >  
> > Here's my routine, I haven't tested the throughput
> >
> > int SPI_OUT(int data)
> > {
> > int i;
> > int dataIn;
> >
> > dataIn = 0;
> > ClearBit(pSS);
> > for (i = 0; i < 8; i++)
> > {
> > if (data & 0x80)
> > SetBit(pMOSI);
> > else
> > ClearBit(pMOSI);
> > data = data << 1;
> >
> > dataIn = dataIn << 1;
> > if (ReadBit(pMISO))
> > dataIn |= 0x01;
> >
> > SetBit(pSCK);
> > ClearBit(pSCK);
> > }
> > SetBit(pSS);
> >
> > return dataIn;
> > }
> >
> > --- In DynoMotion@yahoogroups.com, Tom Kerekes <tk@> wrote:
> > >
> > > Hi Kevin,
> > >
> > > It would be possible except the FPGA is full.  We could offer custom FPGA configurations except I'm afraid that would be a maintenance/documentation nightmare.
> > >
> > > Maybe an optimized software routine would give you a significant speed up.  Can you post the code you are currently using?  What throughput you are getting?
> > >
> > > Regards
> > > TK
> > >
> > >
> > >
> > >
> > > ________________________________
> > > From: fireup_kev <kliboon@>
> > > To: DynoMotion@yahoogroups.com
> > > Sent: Friday, April 5, 2013 10:44 AM
> > > Subject: [DynoMotion] SPI
> > >
> > >
> > >  
> > > Tom,
> > >
> > > Is it possible to add hardware SPI the the FPGA of the KFLOP (master mode)? I'm using software bit-bag SPI right now and it's a bit slow.
> > >
> > > Kevin
> > >
> >
>

SPI V5-7201.c